1. Field of the Invention
The present invention relates to a data processing system for debugging at least one of source code and object code of a parallel arithmetic device.
2. Description of the Related Art
Currently, CPUs (Central Processing Units) and MPUs (Micro Processor Units) are widely used as processor units that are capable of arbitrarily and flexibly executing various types of data processing. In a data processing system that employs such a processor unit, various types of object code that describes the operation commands for the processing that is to be executed and the data that are the object of processing are stored in a memory device, and the processor unit successively reads the operation commands and data from the memory device and successively executes the designated data processing. Looking at a single processor unit, although this processor unit can execute various types of data processing according to the object code, when executing a plurality of processes or tasks, the processor unit executes these processes successively in order. During this successive data processing, the processor unit must read the operation commands from the memory device, and the high-speed execution of complex data processing using a single processor unit is therefore problematic.
On the other hand, when the data processing that is to be executed is limited to a single type, arranging logic circuits as hardware to execute this type of data processing eliminates the overhead that accompanies the reading of operation commands and allows the high-speed execution of the complex data processing. However, a system that depends upon this type of hardware logic is obviously capable of executing only a single type of data processing that has been determined in advance.
A data processing system that is capable of executing any desired object code can execute various types of data processing, but the high-speed execution of data processing is problematic because the hardware configuration is not optimized for a specific type of data processing. A system that is made up of dedicated hardware for executing specific data processing allows the high-speed execution of this data processing, but is not capable of other types of data processing.
To provide a solution to this type of trade-off, the assignee of the present invention has proposed a parallel arithmetic device as a processor unit in which the hardware configuration changes in accordance with software. In this parallel arithmetic device, a multiplicity of relatively small-scale data processing circuits and interconnection switching circuits are arranged as a matrix, and this matrix circuit is provided with a state management unit.
For each data processing circuit, operation commands are set separately, and data processing is executed separately according to these set operation commands. Each interconnection switching circuit is also separately set with operation commands, and each interconnection switching circuit thus switches and controls the interconnection of the data processing circuits according to the set operation command. Still further, the state management unit, in accordance with object code, successively switches contexts for each operating cycle, these contexts being composed of the operation commands of the above-described plurality of data processing circuits and the plurality of interconnection switching circuits.
This parallel arithmetic device, by switching the operation commands that are set to a plurality of data processing circuits and a plurality of interconnection switching circuits, allows the substantial alteration of the hardware configuration and thus allows the execution of various types of data processing. In particular, the execution of simple data processing in parallel by a multiplicity of small-scale data processing circuits enables the execution of high-speed data processing. Further, the switching of contexts by the state management unit enables the parallel arithmetic device to continuously execute parallel processing in accordance with object code. This type of parallel arithmetic device is described in, for example, Japanese Patent Laid-Open Publication No. 2000-138579 (JP P2000-138579A) corresponding to U.S. Pat. No. 6,424,171, Japanese Patent Laid-Open Publication No. 2000-224025 (JP P2000-224025A) corresponding to U.S. Pat. No. 6,281,703, Japanese Patent Laid-Open Publication No. 2000-232354 (JP P2000-232354A) corresponding to U.S. Pat. No. 6,339,341, Japanese Patent Laid-Open Publication No. 2000-232162 (JP P2000-232162A) corresponding to U.S. Pat. No. 6,356,109, Japanese Patent Laid-Open Publication No. 2003-76668 (JP P2003-76668A) corresponding to U.S. Patent Application Publication No. 2003/0046513, Japanese Patent Laid-Open Publication No. 2003-99409 (JP P2003-99409A) corresponding to U.S. Patent Application Publication No. 2003/0061601, and Lawrence Snyder, “Introduction to the Configurable, Highly Parallel Computer,” IEEE Computer, Vol. 15, No. 1, January 1982, pp. 47-56.
In the above-described parallel arithmetic devices, a state management unit successively switches contexts that are contained in object code for each operating cycle, whereby a plurality of data processing circuits and a plurality of interconnection switching circuits that are arranged in a matrix form can perform parallel operations for each operating cycle in accordance with the contexts. However, both the configuration and operation of a parallel arithmetic device differ fundamentally from a conventional CPU, and as a result, simple debugging of the object code and/or source code by a conventional method is no longer possible.